3D IC designed from the AI up.
The Surface EDGE Processor is a 3-die 3D IC semiconductor designed to run Surface natively, on-chip, with no external compute dependency.
Silicon partner programme →Three dies. One architecture.
3nm Logic Layer
Triple ARM Cortex-R82 at 3.0GHz. DSP Geode execution arrays. PCIe Gen 5, GbE, Wi-Fi, Bluetooth. 45W peak TDP.
4nm SRAM Layer
500MB KV step cache. 708MB Foundation ROM. IBM Granite 4 (350M) weights. Mask-programmed at the via layer.
5nm STT-MRAM Layer
1GB cognitive substrate. Learns on-chip through operational use. No cloud write-back. Survives power loss.
88–92% production yield
Manufacturing defects are mapped at the factory. Surface routes around them at runtime. Yield improves from 60% raw to 88–92% production. Every chip shipped works.
This is a runtime architecture decision — the same deterministic execution model that governs Surface AI output governs chip-level fault tolerance.
Silicon programme phases
- Phase 1 — MCU prototype (180–65nm). Functional Geode on standard MCU silicon. Target: H1 2026.
- Phase 2 — Full Geode chip (65–40nm). Complete 3D IC stack. Production-intent silicon. Target: Q1 2027.
- Phase 3 — Sector Geode modules. Application-specific variants. Licensing programme open.